In order to realize even smaller feature sizes in semiconductor technology, techniques for increasing the resolution, i.e., resolution enhancement techniques, RET, are increasingly being used. In this case, primarily innovative mask techniques are used besides structure-specific illumination methods. Alternating phase masks, in particular, have a high lithographic potential, so that it is therefore expected that they will be used to an increased extent in the future.
One problem associated with the novel lithographic methods is based on the fact that the optics of modern lithographic projection systems have non-negligible aberrations despite their high imaging performance. Aberrations are, for example, a consequence of minimal surface inaccuracies of individual lenses in the projection systems used for the transfer, or tiny misalignments of the lenses in relation to one another and also extremely small lens tilting errors relative to the optical axis. This has the effect that semiconductor structures in the vicinity of the limiting resolution, i.e., with a period of at most 0.8*λ/NA, where λ is the wavelength of the light used for the exposure and NA is the numerical aperture of the objective used for the exposure, suffer a positional deviation from a desired position which differs significantly from the positional deviation of the customary overlay error measurement structures, caused by reason, e.g., of inaccuracies during the alignment of semiconductor substrates during the progressive exposure process. The deviation, as determined by overlay measuring devices, of a standard measurement mark generally used for determining the overlay error from the desired position, does not reproduce the actual positional deviation of the circuit structures to be transferred.
Calculation of corrections for the alignment is beset by errors. This in turn has the effect that although after the required corrections have been carried out, the standard measurement marks have small deviations from the desired position and thus satisfy the desired specifications, the circuit structures that are actually of interest are subject to a significant overlay error. This in turn leads to effective losses of yield and to higher costs for component manufacture.
Marks for determining the mutual overlay error of structures of two patterned layers are generally also referred to as overlaying measurement marks.
For example, FIG. 9 shows a detail from an alternating phase mask for patterning holes for making contact with gates in a process for fabricating DRAM (dynamic random access memory) cell arrays. In comparison with conventional halftone phase masks, such a mask enables a significant improvement in the process window and consequently a better structure resolution.
FIGS. 1A and 1B show a customarily used grouping of standard measurement marks respectively in dark and bright field versions. These conventional standard measurement marks have four outer rectangular bars, arranged along the periphery of an imaginary first square, for a first lithographic plane or mask and also four further inner rectangular bars, arranged along the periphery of an imaginary second square, which is arranged concentrically with and parallel to the first square, for the subsequent photolithographic plane or mask, for example, the gate contact-making plane shown in FIG. 9. The outer bars typically have a width of 1.5 μm, while the inner bars have a width of 0.75 μm. In this case, the assignment of the bars to a lithographic plane may also be interchanged, of course.
Usually, the standard measurement marks are arranged at predetermined image field points, typically for each image field at the four corner points and in the center, in the sawing kerf between adjacent chips and are removed after singulation of the wafer with the sawing kerf.
FIG. 10 shows 8 circuit patterns of DRAM chips as are shown as a detail in FIG. 9. The circuit patterns are projected into the image field from a mask. The chips (white areas) are separated by sawing kerfs illustrated by the lines in FIG. 9. The length of the vectors illustrated in FIG. 10 specify the overlay error in the image field, which was measured at the standard measurement marks as shown in FIG. 1, and at the circuit structures, as shown in FIG. 9 in the image field. The large difference, particularly in the upper image field region, is clearly evident. The deviation between the overlay error measured at the standard measurement marks and the actual overlay error of the circuit structure is thus also dependent on the measurement position in the image field. The overlay errors determined at standard measurement marks with the available overlay measuring devices thus describe extremely inaccurately the error that occurs in the component. As a consequence, this error is not detected and corrected accurately enough.
When using special illumination methods, the problem additionally arises that the positional deviation from the desired position depends on the illumination mode. A different positional deviation on the semiconductor substrate is established depending on whether, for example, annular illumination, dipole illumination, or quadrupole illumination is used.
A known test structure arrangement for determining an overlay error, for example, has two grating patterns rotated through 90° with respect to one another. One grating is provided for measurement with respect to the x direction and the other for measurement with respect to the y direction. Thus, x and y standard measurement marks are different from one another and, consequently, also have Fourier spectra that deviate from one another. In the case of the grating structures, spacing and line width are identical and correspond to the minimum line width on the semiconductor substrate. One part of each grating pattern is arranged in a first layer and the other part is arranged in a second layer. The orientation of the other part is measured with respect to the first layer. In order to determine the overlay error, the grating structure is resolved by the measuring system.
A method for detecting and for reducing an overlay error between circuit structures of different lithographic planes is desirable. In particular, an increase in the yield of component fabrication and a reduction in the costs along with reducing the influence of optical imaging errors on the alignment of semiconductor substrates during lithographic projection is desirable.